I2C: Being a Master

During my studies at university, the low level aspects of implementing I2C was not required, and I was too busy (or lazy) to look at the details of the bus. In interviews, when asked, “Do you know I2C?”, I would smile and nod, but deep inside, that hole, where I2C knowledge needed to be filled, grew. Sleepless nights, plagued with excessive drinking of caffeine and lamentation of the deeper meaning of I2C led me to embark on a journey, nay a discovery, of what I2C really is, and how to make a master module.

I2C, or Inter-integrated Circuit, is a two line bus that allows multiple masters to communicate with multiple slaves. The lines used include SCL ( or clock), SDA (or data), and it holds both of these lines high for idle operation. The start, stop, and data levels are all relational to the state of SDA and SCL, specifically the value of one line as another is changing.

For a start condition, the SCL line is high, while the SDA line is driven low. Stop conditions reverse the SDA change, driving it from low to high when SCL is high. All bit transmission requires SDA to change while SCL is low, so that neither condition is triggered accidentally. For a regular transmission of I2C, look at the below graph.

The above image was taken from the SLVA704 document made by Texas Instruments. It does a way better job explaining I2C than this terribly written post.

Great. We have a visual representation of how bytes should be sent, in what order, and how to do write and read conditions. If you’re a sane person, you’ll just make a satisfied nod, as you use whatever API function available to write and read I2C data, and stop reading this post. However, if you’re a masochist, you might ask yourself, “How could I implement this in Verilog?”

Welcome dear masochist, here we begin on a quest! To start our epic adventure, we need to set up our goal: developing an I2C master module for a slave device. I’m using the ADT7420, since it’s a temp sensor on my development board. In the specification sheet of your target device, there should be an “I2C Timing Specification”, which tells the developer how long to hold the SDA line per bit, and the minimum times needed to wait before generating SCL after a start condition, ect. Below is a screenshot from the ADT7420 Specification sheet, visually showing it’s different time based holds and setup times for I2C information.

Look at all those pretty dotted lines

All those barely readable labels next to the arrows are associated with a table, denoting the minimum, and maximum times for clock duration, holding data lines for a bit, and start and stop conditions. Additionally, it tells the developer the minimum and maximum speed for SCL. Since I’m already painted head to toe in red, I know this needs to go blazing-ly fast (WH40K Orks reference anyone?) so lets choose a 400KHz SCL speed.

Since all the timing requirements are based on a time unit (usually microseconds for my device) we need to set a relationship between a counter, and the time it takes for it to increment. I lucked out on my board, with a 100MHz reference clock, it’s easy to divide it to 400KHz. If you’re iffy on the math, to find the amount of clocks needed to go from one clock speed to another, notice 100MHz means 100*10^6 /second, with 400KHz meaning 400*10^3/ second. If you invert 400KHz, and multiply it with 100MHz, you will find the number of clocks needed to convert between the two speeds (250 clocks). Note that this calculated time describes the number of clocks in 100MHz, at which a full period would have occurred in a 400KHz clock. A period consists of the full rise and fall time, meaning we must divide our found number by 2, and invert the output 400KHz clock at these 125 clock markers.

always@(posedge i_clk or negedge reset_n) begin
        {clk_i2c_cntr, clk_i2c} <= 17'b1;
    else if(!en_scl)
        {clk_i2c_cntr, clk_i2c} <= 17'b1;
    else begin
        clk_i2c_cntr <= clk_i2c_cntr + 1;
        if(clk_i2c_cntr == DIV_100MHZ-1) begin
            clk_i2c <= !clk_i2c;
            clk_i2c_cntr <= 0;

Notice that for the above code, an enable is utilized in conjunction with the async reset, as we don’t want our SCL line to continuously be running. We need to know the state of SCL in order to safely operate a state machine around it’s high and low state. Notice here the initial conditions, when driving the SCL line, I’m keeping it high, with the counter equal to 0. This is to ensure that when we are starting I2C, the slave won’t see the SCL line pulled low before a start indication occurs.

With the 400KHz clock written with an enable, we can construct a method to send and receive information from the slave per posedge of the input 100MHz clock. Note that 400KHz is much slower than 100MHz, so we’ll need a few registers to signify when the SCL line has gone high or low.

always@(negedge i_clk or negedge reset_n) begin
    if(!reset_n) begin
        {sda_curr, sda_prev} <= 0;
        {scl_curr, scl_prev} <= 0;
    else begin
        sda_curr <= {sda_curr[0], sda_o};  //2 flip flop synchronization chain
        sda_prev <= sda_curr[1];
        scl_curr <= clk_i2c;
        scl_prev <= scl_curr;

Note, that for SDA, there is a shift register with the sda_o line, which is the modules input pin for SDA. Since we aren’t synchronous to the data on SDA line when receiving information from slave, we need to take meta stability into account. For the SCL, we are taking this information from a register already synchronous to i_clk, meaning we don’t need to have any synchronization code.

Using the previous and current state, we can write a quick if statement determining if the line has gone high, or gone low. Once that occurs, monitor the clk_i2c_cntr for the time needed to meet timing constraints with the slave device, and then move to the next state required by the FSM.

The rest of the code is just state machine maintenance, and simulation testing to ensure you didn’t make any terrible mistakes to cause your FPGA to silently scream into the abyss. If the coding gods don’t smile upon you, or if you just don’t want to deal with coding up all the state transitions and input outputs, here is a link to my implementation:

Notes On Semiconductors: PN junction Practice Problems

Problem 1

An abrupt silicon pn junction has dopant concentrations of Na = 1×10^15 cm^-3 and Nd = 2×10^17cm^-3. (a) Evaluate the built in potential at room temperature. (b) use the depletion approximation to calculate the width of the space-charge layer and the peak electric field for junction voltages Va = 0V, -10V

Turn on voltage

Part b is now asking for the width, W, or referred to as xd. The formula for peak E field and width are below. Note, that epsilon in this equation refers to that of silicon (11.68*8.85*10^-14F/cm). Also note that we must convert this constant to cm in order to use it in the problem

Width of depletion//space charge region

Maximum field based off of V = (1/2)Emax*xd

Solving for both conditions we find xd = 0.97um for 0V and 3.73um for -10V, with E field being 14800V/cm for 0V, and 57500V/cm for -10V.

Problem 2

Find and sketch the built in field and potential for a silicon PIN junction with the doping profile shown. Indicate the length of each depletion region.

To begin solving part a, we must look at the charge densities of each region, and use Poisson’s equation in order to establish a relationship between x, field, and potential. To do this, we will create 4 ticks on the x axis, x1 being somewhere to the left of -1, x2 = -1, x3 = 0.5, and x4 being somewhere beyond x3.

charge density on n-side is equal to qNd

only valid for this boundary condition

Final potential for N-side

Notice due to having no doping in this middle region, we can say that the charge density is 0, thus E through this region has to relate to the field generated by the n-type

Boundary for intermediate region

Note that we are using the potential of where we started when integrating

Final for middle region

Notice that charge density is equal to -qNa, thus the bounds were flipped

Here we see what we are integrating from, and what our bounds will be

Here is final equation

Here we are defining the max fields we need

Relationship of turn on voltage and the 3 zones of potential

Additionally, we know that the vbi is the same for a pn junction in this problem, thus

Note Vbi is the same as phi subscript i

Note here that due to emax, we are able to make a relationship between (x2-x1) and (x4-x3), which our two depletion region zones

To answer this question, we use the equation relating to doping concentrations and turn on voltage to find the turn on voltage, and our relationship between the two depletion regions in order to solve for one. I chose to solve for the (x2-x1) first, using my calculator to solve the quadratic formula. Remember boltzmann’s constant is 8.617*10^-5ev/K, the e and q cancels, and epsilon is equal to 11.68*8.85*10^-14F/cm for silicon, and temperature is in Kelvin. Final answer to (x2-x1) is 2.5*10^-6cm. Using the relationship of the depletion regions, we solve (x4-x3) = 2.5*10^-4cm. Graphing all the fields should be trivial after obtaining these values. The following equation is a visual representation:

Final equation

b. Compare the maximum field to the field in a pn junction that contains no lightly doped intermediate region but has the same dopant concentrations.

Note: for PIN junction only

Maximum field based off of V = (1/2)Emax*xd. This is for abrupt PN junction

Note from above problem that width is equal to ((2eps/q)*(NaNd/(Na+Nd))*(Vi-Va))^1/2

Using the pin junction we solve for a value of 3869 V/cm. Assuming same doping concentrations for pn junction, we solve to find width equal to 9.48*10^-5cm, and Emax = 13354.43V/cm

c. Explain what is happening

Due to the middle region between the p and n type material that holds no doping concentration, voltage is dropped. The reduced voltage induces a smaller depletion region on either material, which is directly related to electric field. Due to the reduced voltage, it makes sense that the electric field would drop in the pin junction.

d. Discuss how the depletion capacitance

To solve for capacitance, we must make a relationship of C = d(Q)/dVa, and Q is equal to (x2-x1). Thus we can use the final equation used to solve part A for this. Taking the derivative with respect to Va will give you the following equation

Taking derivative of x2-x1 in respect to Va.

Final equation

This equation is only differing from a regular p-n junction by one term relating to the lightly doped region. Due to this term, the capacitance is much lower due to the depletion region being wider.

Capacitance of a pn junction

Problem 3

Problem 3

Assume that the dopant distributions in a piece of silicon are indicated above. (Na0 = 10^18cm^-3, x0 = 10^-4cm unless otherwise indicated, lambda a = 10^-4cm, and lambda d = 2*10^-4 cm)

a. If the pn junction is desired at x0 = 1um, what should be the value of Nd0?

We know that at x0, Na = Nd,  thus,



Equation to Solve part A

Using the second equation, we find that Ndo = 6.1×10^17cm^-3

b. Assume the depletion approximation and make a sketch of space charge near the junction. Approximate this space charge as if this were a linearly graded junction.

Now with part b, we are using x0 = 10^-4cm. Due to the fact that they said linearly graded junction, we know immediately that the charge density will be equal to q(Nd-Na) = qa(x-x0)

Noting this relationship, we are tasked to approximate the linearly graded junction at the intersect. Therefore, we must take the derivative of (Nd-Na) as x approaches x0.

Answer to problem

Plugging in the found value for Ndo, and x0 = 10^-4cm, we find that a = 1.83×10^21cm^-4

c. Under the approximation of part B, take turn on voltage = 0.7V to calculate Emax at thermal equilibrium. Using:

Width of linear junction

Emax related to voltage in linearly graded junction

Problem 4

The small signal capacitance Cd of a pn junciton diode with an area of 10^-5cm^2 is measured. A plot of 1/Cd^2 vs Va is shown below

a. If the diode is considered as a one sided step junction find the indicated oping level on the lower conductivity side (use the slope)

So here, we know we can relate the doping concentrations with capacitance. We know that Cd = Aeps/xd, and we know that xd is related to both doping concentrations. Assuming a one sided step junction means that one of the concentrations will be considered negligible, thus, our equation will simplify into:

Equation relating doping concentration with capacitance

This equation relates the slope that we will find from the graph to doping concentration

Finding the slope is simply (1.5*10^26-0)/(-1-0.8) which gives a negative slope who’s magnitude is 8.33*10^25F^-2V-1. Using this slope with the other values given (recall that eps in silicon is 11.68*8.85*10^-14F/cm. Once solved, we find that N = 1.45*10^15cm^-3

b. Sketch the doping density on the low conductivity side of the junction. Calculate the location of any point at which the dopant density changes.

Here we use the same equation of Cd = Aeps/xd, however, we rearrange it to xd = Aeps/Cd. We know that at the lowest conductivity, Cd will be at its highest on the graph. Thus, we know Cd = (1.5*10^26)^-1/2, and we solve for xd, which equals to 1.27um.

c. Use the intercept on the (1/Cd^2) plot to find the doping density on the highly doped side.

Here we must use a specialized equation relating doping concentration and built in turn on voltage. The x intercept is of interest here, as it is the turn on voltage. Vbi = 0.8V. Using this eqn:

Note, the ni^2/N is relating to the eqn n*p = ni^2

Solving this equation we find Nother = 3.34*10^18

Problem 5

To treat avalanche from first principles, consider than an incident electron collides with the lattice and frees a hole-electron pair. Assume after the interaction, the three particles share the same kinetic energies. Also assume all have the same mass. Use conservation of energy and momentum principles to find that the threshold occurs at (3/2)Eg units of kinetic energy.

So this problem is simply physics. We know that initially we have 1 electron, and at the end we have 2 electrons and one hole. Thus, Ei = Eg + 3Ef, and mvo = 3mvf. Using the momentum conservation equation, we find that vf = 1/3v0. Knowing this is kinetic, know that Ei = 1/2m(vo)^2, and Ef = 1/2m(vf)^2. Substituting we find that

1/2m(vo)^2 = Eg+1/6m(vo)^2; moving to like sides we find -> Eg = 1/3m(vo)^2, thus m(vo)^2 = 3Eg. Finally relating this to Ei, divide both sides by two to find

Ei = 1/2m(vo)^2 = (3/2)Eg

Problem 6

Is Zener breakdown more likely to occur in a reverse-biased silicon or germanium pn junction diode if the peak electric field is the same in both diodes? Discuss. (Consider Band Gap)

Zener breakdown is attributed to the tunneling effect, therefore the smaller band gap in germanium would allow for a zener breakdown at a certain electric field over the silicon junction.

Notes on Semiconductors: P-N junctions: Linearly Graded Regions

After taking a look at abrupt junctions, we can now move onto linear graded junctions. To solve for the equations relating positioning, doping, field, and potential, we shall be using Poisson’s Equation:

Poisson Equation

For linearly graded junctions, the graphs look like this:

Due to the symmetry of linearly graded junctions, we can equate xn = xp = xd/2. Based on this assumption, we can begin to solve for the turn on voltage, the electric field based on position x, and the potential based on x. First we will find the turn on voltage.

Relating holes with the linear graded limit

Rearranging Equation

Relating linear with electrons

rearranging eqn

Solving for Vbi


Once we have derived the turn on voltage, now we must relate the electric field based on what point you are in the linearly graded region.

Finding charge density

Setting up Poisson

Integrating Poisson

Solving for C

Finished Linear Electric Field

Now with the electric field found, we must now solve for potential. Note, that potential is equal to the negative integral of the electric field

Potential relating to integral of E field

Finished Equation for Potential

Width of linear junction

For capacitance, it is the same as abrupt junctions:

Notes on Semiconductors: P-N junctions

Familiar with P-type semiconductors and N-type semiconductors, coupled with the basic ways to calculate their values for holes and electrons, we can now move onto the next subject: P-N junction diodes. Diodes are shown by the following figure, and are characterized by allowing current to flow through them only if the voltage drop is greater than their turn on voltage. The diode will resist all current flow when the voltage dropped across its terminals are below the turn on voltage. The voltage dropped by the diode can usually be characterized by approximately 0.7 V, i.e., Vanode-Vcathode = 0.7V. The 0.7V is an example of a turn on voltage. If the voltage was less than this value, there would be no current flow.

This is what a schematic for a diode looks like

Now, we must take a look under the hood of the diode, with the equations we currently know, to understand what physics determine our specified behavior. When a PN junction diode is created, there is a point where the two semiconductor material meets, and allows for a flow of electrons. Eventually, a equilibrium state is reached, at which point there is a space in the P side that is negatively charged (due to its doping atoms accepting electrons from the N type semiconductor’s donors), and conversely a space in the N side is positively charged. Remembering basic physics, we know that a separation of charges will create an electric field pointing from the positive charges to the negative charges. Recall that E = -grad(V).

Representation of PN junction fields from Wikipedia

Noticing this orientation, and direction of the electric field, one could wonder, what side of the PN junction is the cathode and anode? (Answer, the voltage drop has to overcome the electric field direction, thus the P side is the anode, and the N side is the cathode)

Now, it is important to create a relationship between the concentration of the doped atoms in either semiconductor, and the voltage needed to overcome the electric field to turn the device on. All of these variables will also be used to determine the length of the space charged region in either semiconductor.

Note the direction of the electric field in the diagram of a PN junction, and recall E = -grad(V), thus as the electric field increases, the voltage will decrease. Using this principle we can estimate that:

Generic Equation to base Vbi

Equation to find holes based of Fermi level

Rearranged Equation

Relationship between Fermi level and Voltage

Donor equation and Fermi level

Voltage at n side in respect to fermi level

Finished Equation

Note: The equations used in this post are for ABRUPT junctions. The graphs for abrupt junctions look like this:

Using the equations relating to holes and electron density in the semiconductor materials, we can derive the final equation to find the amount of voltage needed to turn the diode on. NOTE: the holes concentration and electron concentration are different in the two semiconductors, meaning it does not hold true that the doping concentration of the p-type, multiplied by the doping concentration of the n-type will equal the intrinsic concentration squared. That is, the two semiconductors have two separate equations to find the concentrations of holes and electrons.

With a relationship describing the turn on voltage, now we must create a relationship with the doping concentrations, applied voltage, turn on voltage, and depletion region width.

Using the Poisson Equation, we can make a relationship between the electric field (V/cm), the charge density (C/cm^3) and the permittivity (F/cm)

Poisson Equation

Gradient of Electric field for n-type

Gradient of Electric field for p-type

Now we have established what the gradient of the electric field for both sides of the PN junction in the depletion region. The xn and xp are the boundaries of the depletion (or charged) region. To make a relationship between this equation and electric field, we must integrate this equation. Due to the fact that we are only concerned with the gradient in the x direction, we are only mentioning the x direction in respect to voltage. Recall a gradient is equal to partial derivative x (i) + partial derivative y (j)+ partial derivative z (k).

Representation of PN from Solid State Electronic Devices 6th edition

The reason for the bounds is due to the fact we are integrating from Electric field max to the electric field where it is 0 (boundary)

Integrating on p-type

Graph representing where Emax (Eo) from Solid State Electronic Devices 6th edition. At boundary xp, or xn, electric field must equal zero

Finding maximum electric field

Final relationship between xn and xp

With the relationship with electric field found, we must integrate again to find the relationship of the doping concentrations and voltage. Due to electric field being equal to the -grad(V), we know that the turn on voltage has to be equal to the electric field integrated from xp to xn. To find this value, we should take our previously derived equations for electric field along the p and n ranges, integrating them to find their associated voltage value.

Relationship between E and V on p-side

Relationship between electric field and potential on p-side

Final for p-side in an abrupt junction

Integrating the N side we will find:

Relationship Between E field and Potential

Final Relationship for an abrupt junction

To solve for the charged region aka depletion region, all one must do is set the equation to x = 0, where both p-type and n-type will equal each other.  Thus:

Setting eqn to Zero


Relationship between turn on voltage and Electric field max using relationship of left equation and xn and xp

Definition of Width

Final equation to determine with of space charge region


Notes on Semiconductors: An Introduction

Preparing for a new semester, I’ve decided the best way to keep all my notes intact is to add them here to a website. My notes for semiconductors for example, are scattered upon 3 different textbooks and I’m personally annoyed to carry so much useless weight.

And so it begins:

Semiconductors are initially created from a metal, and is usually doped in order to allow a gradient that current can flow through. An INTRINSIC semiconductor is an un-doped material at which the statement n = p = ni is true.

Further explanation of n, p and ni: n stands for electrons that can be broken from their molecule and moved. p stands for holes which can be filled by electrons. ni is the material specific intrinsic carrier concentration. In a doped semiconductor, the equation n*p = ni^2
If doped with DONORS, the concentration Nd = n, if doped with ACCEPTORS, the concentration Na = p. If both were used the concentration depends on type. n = Nd-Na, p = Na-Nd.

With the general concept of holes, electron concentration, and doping covered, next is deriving a relationship between the energy band spectrum of the semiconductor and inferences to its type and concentrations. Normally, the intrinsic carrier concentration is known for the element, so solving for the type, and concentration of doping element is usually the problem structure.

Example of a band diagram

Note only the conduction band (Ec), Fermi level (Ef), the intrinsic level (Ei, which is in middle of band gap), and Valence band (Ev). In these semiconductor problems, you can identify the type off semiconductor by where a band labeled Ef is placed. If Ef is ABOVE Ei, then the semiconductor is N-type, if it is below Ei, it is P-type.

Now for the equations that relate to this->

Slides taken from: A.R. Hambley, Electronics, © Prentice Hall, 2/e, 2000 A. Sedra and K.C. Smith, Microelectronic Circuits, © Oxford University Press, 5/e, 2004


Note: K is the boltzmann constant (𝑘=8.62×10−5 eV/K) and T is temperature in Kelvin

Nerdy Modeling

I present Mortarion, Primarch of the Death guard legion.

I promise it looks much better in person; my phone’s camera is a potato.

Front View

Back View

Keep in mind, this is what it looked like 40 hrs previously: