`timescale 1ns/1ps

/*
* Chance Reimer
* Implemented circuit from 
* Date 8/30/2018
* Def: used for each button to ensure that the counter goes up by one, and that the button press will not exceed 3 presses for all the different modes
*/

`timescale 1 ns / 100 ps
module  deBounce 
	(
	input 			clk, n_reset, button_in,				// inputs
	output reg 	DB_out													// output
	);
//// ---------------- internal constants --------------
	parameter N = 20 ;		// (2^ (21-1) )/ 38 MHz = 32 ms debounce time
////---------------- internal variables ---------------
	reg  [N-1 : 0]	q_reg;							// timing regs
	reg  [N-1 : 0]	q_next;
	reg DFF1, DFF2;									// input flip-flops
	wire q_add;											// control flags
	wire q_reset;
//// ------------------------------------------------------

////contenious assignment for counter control
	assign q_reset = (DFF1  ^ DFF2);		// xor input flip flops to look for level chage to reset counter
	assign  q_add = ~(q_reg[N-1]);			// add to counter when q_reg msb is equal to 0
	
//// combo counter to manage q_next	
	always @ ( q_reset, q_add, q_reg)
		begin
			case( {q_reset , q_add})
				2'b00 :
						q_next <= q_reg;
				2'b01 :
						q_next <= q_reg + 1;
				default :
						q_next <= { N {1'b0} };
			endcase 	
		end
	
//// Flip flop inputs and q_reg update
	always @ ( posedge clk )
		begin
			if(n_reset ==  1'b1)
				begin
					DFF1 <= 1'b0;
					DFF2 <= 1'b0;
					q_reg <= { N {1'b0} };
				end
			else
				begin
					DFF1 <= button_in;
					DFF2 <= DFF1;
					q_reg <= q_next;
				end
		end
	
//// counter control
	always @ ( posedge clk )
		begin
			if(q_reg[N-1] == 1'b1)
					DB_out <= DFF2;
			else
					DB_out <= DB_out;
		end

endmodule


/*

module debouncer_LED(input clk,
		     input rst,
		     input  buttonPress,
		     output reg buttonPressedValid);

	wire en_clk2;
	reg _Q1,_Q2,Q2_bar; //outputs to flip flops
	
    always_ff@(posedge clk)
    begin
        if(rst)
        begin
            buttonPressedValid <= 0;
            Q2_bar <= 0;
        end
        else
        begin
            Q2_bar <= ~_Q2;
            buttonPressedValid <= _Q1 & Q2_bar & en_clk2;
        end
    end
	//assignment of slower Clk
	enable_press u1(.clk(clk),
		        .buttonPress(buttonPress),
		        .rst(rst),
			.en_clk2(en_clk2)); 
	
	//First D flip Flop
	d_FF d1(.clk(clk),
		.enable_clk(en_clk2),
		.D(buttonPress),
		.Q(_Q1),
	        .rst(rst));
	//Second Flip Flop
	d_FF d2(.clk(clk),
		   .enable_clk(en_clk2),
		   .D(_Q1),
		   .rst(rst),
		   .Q(_Q2));

//	assign Q2_bar = ~_Q2;
//	assign buttonPressedValid = _Q1 & Q2_bar & en_clk2;
endmodule

/******************************************
* Helper modules


// Slow clock enable for debouncing button 
module enable_press(input clk,	
		    input buttonPress,
		    input rst,
		    output en_clk2);

    reg [26:0]counter;
    always_ff @(posedge clk or posedge rst)
    begin
     if(rst)
              counter <= 0;
            else
       counter <= (counter>=2499)?0:counter+1; //249,999
    end

    assign en_clk2 = (counter == 2499)?1'b1:1'b0; //249,999
endmodule

// D-flip-flop implementation
module d_FF(input clk,
	    input rst,
            input D,
       	    input enable_clk, 
	    output reg Q);

    always_ff @ (posedge clk or posedge rst) 
    begin
	if(rst)
		Q <= 0;
  	else if(enable_clk) 
		Q <= D;
    end
endmodule 

*/